Design of Ka-band CMOS stacked power amplifier with temperature compensation

This paper presents a Ka-band stacked high-efficiency power amplifier(PA) with a temperature compensation circuit in 55 nm CMOS technology. A novel temperature compensation circuit for the stacked PA is proposed. The compensation circuit consists of two diodes and four resistors which is easy to implement. By optimizing the gate voltage of each layer in the bias circuit of the stacked PA, the gain and output power of the stacked PA with temperature variation are effectively compensated, which enhances the reliability and thermal stability of the circuit. The simulation results based on Agilent ADS software show that the maximum output power is 20.1 dBm, 20%-30% of power added efficiency (PAE) is achieved in the entire band, and the large signal power -1 dB bandwidth is 15 GHz (46%). The temperature fluctuation of the small signal gain is improved from 2.2 dB to 0.1 dB in the temperature range from -40 ℃ to 125 ℃ compared with conventional bias circuits. It has been demonstrated that the presented temperature-compensation circuit is effective for correcting gain variation of a power amplifier in a wide temperature range.