Analysis of thermal stress effect on the electromagnetic immunity ofdigital logic circuit's GPIO

Due to the electromagnetic immunity drift problems of integrated circuit in complex electromagnetic environment, we study the influence of ambient thermal stress on the GPIO electromagnetic immunity of typical digital logic circuit. The typical FPGA GPIO electrical topology structure and the disturbance mechanism of electromagnetic-thermal coupling stress on internal MOS devices is analyzed. And the environmental thermal stress interference factor is introduced into the prediction and analysis of electromagnetic immunity and the conducted immunity-thermal effect model ICIM-CI-T is built which is based on the integrated circuit electromagnetic conducted immunity model ICIM-CI. Then, the immunity test platform based on direct power injection of electromagnetic interference coupled with thermal stress is designed and the immunity threshold curve of simulation and measurement is obtained. The result show that the simulations are consistent well with the measurements within the frequency range of 10 MHz-1 GHz. During the ambient thermal stress is changed from 20℃ to 100℃, the thermal stress seems to have no effect on the immunity of GPIO when the frequency is less than 200MHz, and it decreases with the increase of thermal stress interference within the frequency range of 200 MHz-700 MHz, especially, the immunity threshold decreases by 4 dBmw at 300 MHz and 600 MHz.