Design of CMOS active phase shifter based on single-sideband time-modulation

To meet the requirement of low-cost phased array for high-precision beam scanning, the design of CMOS active phase shifter based on single-sideband time-modulation (STM) is proposed in this paper. Based on Global Foundries 0.13 μm CMOS process, a bi-phase modulator is designed for 0°/180° phase shifting of I/Q channels to suppress the fundamental frequency and even-order sidebands from time modulation. A vector synthesis stage followed by a current-reused amplifying stage is designed to improve the gain without increasing power consumption. The bias and timing control units are designed to realize the STM by the timing control of the gains of I/Q channels. The simulation results show that the total power consumption is 15.8 mW from the 1.8 V supply, and its gain is −3±1.5 dB in the 3-dB bandwidth (13.2−20.7 GHz). In the frequency band of 10−25 GHz, the root mean square (RMS) phase error is less than 0.1°, the RMS gain error is less than 0.02 dB, and the phase resolution can reach more than 10 bits. The maximum unwanted sideband (−7th sideband) has a power rejection ratio of 16.7 dBc. The proposed active phase shifter has the properties of low cost, low power consumption, low phase and gain errors and low insertion loss, which provides a novel topology for the time-modulated array.