Abstract: A design method of wideband low phase noise frequency synthesizer is proposed in the paper. Digital phase locked loop(PLL) technology is adopted. The frequency synthesizer is mainly composed of PLL chip, active loop filter, wideband voltage controlled oscillator (VCO) and external wideband divider. The PLL can realize any frequency output in 10-20 GHz. And it has the advantages of wide output frequency, low phase noise, high integration, low power consumption and low cost. The phase noise test curves are presented, and the experimental results show that the phase noise of the PLL is better than that of -109 dBc/Hz@1 kHz when the output is 10 GHz, which is very close to the phase noise of the direct frequency synthesizer.